1. Field of the Invention
This invention relates to a random access type semiconductor memory device, and more particularly, to a semiconductor memory device having a redundant circuit for replacing a defective memory cell included in memory cells of a main memory cell array by a memory cell in a spare memory cell array for each unit of word line, that is, replacing the defective memory cell and memory cells connected to the same word line to which the defective memory cell is connected by memory cells connected to the same spare word line in the spare memory cell array.
2. Description of the Related Art
In the random access memory (RAM), as the memory capacity becomes larger, the possibility that a redundant circuit for relieving the defective memory cell is provided becomes higher. The redundant circuit includes a spare memory cell array having memory cells with the same construction as memory cells in the main memory cell array. In a case where defects occur in the memory cells of the main memory cell array or word lines, the memory cells connected to the same word line to which the defective memory cell is connected or the memory cells connected to the defective word line are replaced by the memory cells connected to the same spare word line in the spare memory cell array so as to relive the defective memory cell array, thus enhancing the manufacturing yield.
In order to permit the memory cells in the spare memory cell array to be selected instead of the memory cells in the main memory cell array, a plurality of programmable elements such as fuses are provided in the redundant circuit, and whether the redundant circuit is used or not is determined according to whether at least one of the fuses is cut off or not and a row address for the defective memory cell or defective word line is programmed by selectively cutting off the fuses. When a row address for a word line to which the defective memory is connected or the defective word line is input, one of the spare word lines is selected based on the program made by use of the fuses. At this time, all of the word lines in the main memory cell array are set in the non-activated state, thus permitting the spare memory cell in the spare memory cell array to be selected instead of the memory cell in the main memory cell array.
The conventional RAM having the above redundant circuit is constructed as shown in FIG. 1. An address signal constructed by row and column addresses for selecting a memory cell is supplied to an address buffer circuit 15. An output signal of the address buffer circuit 15 is supplied to row partial decoders 16A and 16B, spare decoder 19 and column decoder 22. The row partial decoders 16A and 16B decode respective internal row address signals output from the address buffer 15 to create partial decode signals. The partial decode signals are supplied to a main row decoder 17. The spare decoder 19 is supplied with an output of a programming circuit 18. The programming circuit 1 has fuses indicating whether or not the redundant function is used and fuses for programming an address for the defective memory cell. The spare decoder 19 decodes an internal row address signal supplied from the address buffer 15 to create a partial decode signal when the programming circuit 18 is programmed to use a redundant function and the programmed defective row address coincides with the above internal row address signal. The partial decode signal output from the spare decoder 19 is decoded by the spare row decoder 20 and the decoded signal is used to select and drive one of spare word lines SWL1 to SWLp. Further, the spare decoder 19 outputs to the main row decoder 17 a control signal R/D which is set to a low logic level when an internal row address signal corresponding to the defective row address is input and to a high logic level when a row address signal other than the internal row address signal is input. The main row decoder 17 decodes the partial decode signals of the row partial decoders 16A and 16B so as to select and drive one of the main word lines MWL1 to MWLm when the control signal R/D is set at the high logic level. On the other hand, when the control signal R/D is set at the low logic level, the main row decoder 17 selects none of the main word lines MWL1 to MWLm, and at this time, the spare row decoder 20 selects and drives one of the spare word lines SWL1 to SWLp.
A main memory cell array 11 is constructed by memory cells 13-11 to 13-mn arranged in a matrix form of m rows.times.n columns. A spare memory cell array 12 is constructed by memory cells 13S-11 to 13S-pn arranged in a matrix form of p rows.times.n columns. Each of the spare memory cells 13S-11 to 13S-pn has the same construction as the memory cells 13-11 to 13-mn. Those of the memory cells 13-11 to 13-mn in the main memory cell array 11 which are arranged on the same row are connected to a corresponding one of the main word lines MWL1 to MWLm and the memory cells 13-11 to 13-mn are selected for each row. Those of the memory cells 13S-11 to 13S-pn in the spare memory cell array 12 which are arranged on the same row are connected to a corresponding one of the spare word lines SWL1 to SWLp and the memory cells 13S-11 to 13S-pn are selected for each row. Those of the memory cells 13-11 to 13-mn and 13S-11 to 13S-pn in the main memory cell array 11 and spare memory cell array 12 which are arranged on the same column are connected to a corresponding one of bit line pairs BL1, BL1 to BLn, BLn. Each pair of bit lines BL1, BL1 to BLn, BLn are connected at one end to a corresponding one of bit line initializing circuits 14-1 to 14-n for initializing the potentials of the pairs of bit lines BL1, BL1 to BLn, BLn. Further, each pair of bit lines BL1, BL1 to BLn, BLn are connected at the other end to a corresponding one of column selection circuits 21-1 to 21-n for selecting the pairs of bit lines BL1, BL1 to BLn, BLn. The input terminals of the column selection circuits 21-1 to 21-n are connected to the output terminal of the column decoder 22 and one of the circuits 21-1 to 21-n is selected according to the decode signal output from the column decoder 22.
FIG. 2 is a circuit diagram showing the detail construction of part of the main row decoder 17 in the RAM shown in FIG. 1. The circuit includes NAND gates 25 and inverters 26. For example, a row address signal is constructed by four bits of X1, X2, X3 and X4 and X1.multidot.X2, X1.multidot.X2, X1.multidot.X2 and X1.multidot.X2 (for example, X1.multidot.X2 indicates an AND logic signal of X1 and X2 and X1.multidot.X2 indicates an AND logic signal of an inverted signal of X1 and X2) shown in FIG. 2 are output signals of the row partial decoder 16A for deriving partial decode signals of the two-bit row address signals X1 and X2. Likewise, X3.multidot.X4, X3.multidot.X4, X3.multidot.X4 and X3.multidot.X4 are output signals of the row partial decoder 16 for deriving partial decode signals of the two-bit row address signals X3 and X4. Selected two of the partial decode signals and the control signal R/D are supplied to a corresponding on of the decoding three-input NAND gates 25. Outputs of the NAND gates 25 are respectively supplied to the inverters 26 serving as buffer circuits and the main word lines MWL are driven by outputs of the inverters 26.
FIG. 3 is a timing chart of signals in the main row decoder 17. As shown in FIG. 3, in a case where no redundant function is provided, the partial decode signals (which are represented by X1.multidot.X2 and X3.multidot.X4 in FIG. 3) rise at time T1 and then the control signal R/D rises to the high logic level at time T2, and after this, the main word line MWL is set to the high logic level at time T3. The time T2 at which the signal R/D rises must be set to a time point after the time T1 at which all of the other partial decode signals rise. This is because a defective word line may be selected or a main word line (which should not be selected) different from a to-be-selected main word line may temporarily be selected and the access time may be delayed by reverse reading of data before a correctly corresponding one of the word lines MWL1 to MWLm is selected in response to an address input if the signal R/D rises earlier than the other partial decode signals. Therefore, the spare decoder 19 is so constructed as to cause the signal R/D to be changed after the partial decode signals have changed, thereby causing the access time of the RAM to be determined based on the control signal R/D. Further, since the control signal R/D input to the main row decoder 17 is supplied to all of the decoding NAND gates 25 as shown in FIG. 2, the load capacitance becomes large and the time for the signal R/D to rise to the high logic level becomes longer (the rate of rise of the signal becomes dull) as shown by the timing chart of FIG. 3. As a result, the access time becomes further longer.
Further, if fall of the control signal R/D is delayed when the access is changed from the main memory cell array 11 to the spare memory cell array 12, multi-selection may occur at this time. If the driving ability of the circuit portion for outputting the control signal R/D is increased to reduce the rise time and fall time of the control signal R/D, a current consumption will increase.